Xilinx Configurable Logic Block

05Jun12

Configurable Logic Blocks (CLB) are programmable elements inside a Xilinx FPGA. The figure shown below depicts FPGA Device fabric which is made up of several CLB’s (Snapshot taken from Xilinx PlanAhead Tool). Each of those boxes inscribed in blue are CLB’s which consists of slices & other components. Virtex-5 CLB A Virtex-5 CLB Tile consists […]

Filed under: FPGA Concepts, VLSI   |  2 Comments
Tags: CLB, FPGA Architectures, FPGA CLB, FPGA Slice, ISE, PlanAhead, Slices, VLSI, Xilinx, Xilinx CLB

Xilinx’s Vivado Design Suite

02May12

It seems Xilinx has released a new Design Suite for FPGA & SoC designs. Is it an ISE replacement? They came out with a press release last week.  Check this link : http://bit.ly/K1yMB2 Watch this space for more 🙂 

Filed under: Trivia   |  Leave a Comment
Tags: EDA, FPGA, ISE, News, Vivado, VLSI, Xilinx

FPGA File Management Tip

02May12

Tips to save disk space Xilinx ISE:  Manual Copy of Sources While migrating from one design to another copy ONLY the source files like vhd, ucf, xco, cdc files (xco refers to Xilinx Coregen file & cdc is related to Chipscope pro). If there are filters don’t forget to move the .coe & .mif  Other files […]

Filed under: FPGA Concepts, Project Management   |  Leave a Comment
Tags: File Management, FPGA, ISE, Mentor Graphics, ModelSim, Simulation, VCD, VLSI, Wave Viewer, Xilinx