Xilinx Configurable Logic Block
Configurable Logic Blocks (CLB) are programmable elements inside a Xilinx FPGA.
The figure shown below depicts FPGA Device fabric which is made up of several CLB’s (Snapshot taken from Xilinx PlanAhead Tool). Each of those boxes inscribed in blue are CLB’s which consists of slices & other components.
A Virtex-5 CLB Tile consists of 2 SLICES. Figure depicts each CLB tile consisting of 2 slices. The components have been labelled for better understanding.
The above snapshot is taken from PlanAhead tool which is part of ISE Design Suite System Edition.
Each slice in a CLB consists of a 6 input LUT, Multiplexers (2:1), Carry logic made up of MUX & XOR gates, and D-Flip flops. All our logic gets mapped into these components using synthesis algorithms.
For more on FPGA architectures watch this space.
Filed under: FPGA Concepts, VLSI | 1 Comment
Tags: CLB, FPGA Architectures, FPGA CLB, FPGA Slice, ISE, PlanAhead, Slices, VLSI, Xilinx, Xilinx CLB