Xilinx Configurable Logic Block

05Jun12

Configurable Logic Blocks (CLB) are programmable elements inside a Xilinx FPGA.

The figure shown below depicts FPGA Device fabric which is made up of several CLB’s (Snapshot taken from Xilinx PlanAhead Tool). Each of those boxes inscribed in blue are CLB’s which consists of slices & other components.

Virtex-5 CLB

A Virtex-5 CLB Tile consists of 2 SLICES. Figure depicts each CLB tile consisting of 2 slices. The components have been labelled for better understanding.

The above snapshot is taken from PlanAhead tool which is part of ISE Design Suite System Edition.

Each slice in a CLB consists of a 6 input LUT, Multiplexers (2:1), Carry logic made up of MUX & XOR gates, and D-Flip flops. All our logic gets mapped into these components using synthesis algorithms.

For more on FPGA architectures watch this space.

About these ads


2 Responses to “Xilinx Configurable Logic Block”

  1. This piece of writing provides clear idea for the new
    viewers of blogging, that truly how too do running a blog.

  2. Do you mind if I quote a couple of your posts as long as I provide credit and sources back
    tto your site? My website is in the very same area of interest as yours
    and mmy users would definitely benefit from some of the information you provide here.
    Pleaee let me know if this aldight with you. Regards!


Feedback

Fill in your details below or click an icon to log in:

WordPress.com Logo

You are commenting using your WordPress.com account. Log Out / Change )

Twitter picture

You are commenting using your Twitter account. Log Out / Change )

Facebook photo

You are commenting using your Facebook account. Log Out / Change )

Google+ photo

You are commenting using your Google+ account. Log Out / Change )

Connecting to %s


Follow

Get every new post delivered to your Inbox.

Join 64 other followers